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Electrical Specifications Subject to Change
LTC2262-12 12-Bit, 150Msps Ultralow Power 1.8V ADC FEATURES
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DESCRIPTION
The LTC(R)2262-12 is a sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2262-12 is perfect for demanding communications applications with AC performance that includes 70.5dB SNR and 88dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include 0.3LSB INL (typical), 0.1LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS. The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
70.5dB SNR 88dB SFDR Low Power: 146mW Single 1.8V Supply CMOS, DDR CMOS or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full-Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm x 6mm) QFN Package
APPLICATIONS
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Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing
TYPICAL APPLICATION
1.8V VDD 1.2V TO 1.8V OVDD
2-Tone FFT, fIN = 68MHz and 69MHz
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80
+
ANALOG INPUT INPUT S/H
-
12-BIT PIPELINED ADC CORE
CORRECTION LOGIC
OUTPUT DRIVERS
D11 CMOS * OR * LVDS * D0 OGND
CLOCK/DUTY CYCLE CONTROL GND
226212 TA01a
-90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60 70
150MHz CLOCK
226212 TA01b
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LTC2262-12 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (VDD, OVDD) ....................... -0.3V to 2V Analog Input Voltage (AIN+, AIN-, PAR/SER, SENSE) (Note 3) ...........-0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC-, CS, SDI, SCK) (Note 4) .................................... -0.3V to 3.9V SDO (Note 4) ............................................ -0.3V to 3.9V
Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Operating Temperature Range: LTC2262C ................................................ 0C to 70C LTC2262I.............................................. -40C to 85C Storage Temperature Range................... -65C to 150C
PIN CONFIGURATIONS
D10_11 SENSE FULL-RATE CMOS OUTPUT MODE TOP VIEW VREF DNC VCM D11 D10 VDD D9 D8 OF DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW SENSE D8_9 DNC VREF DNC DNC DNC 30 D6_7 29 DNC 28 CLKOUT+ 27 CLKOUT- 41 26 OVDD 25 OGND 24 D4_5 23 DNC 22 D2_3 21 DNC 11 12 13 14 15 16 17 18 19 20 CS SDO DNC DNC SCK SDI D0_1 ENC+ ENC- VCM VDD OF
40 39 38 37 36 35 34 33 32 31 AIN+ 1 AIN- 2 GND 3 REFH 4 REFH 5 REFL 6 REFL 7 PAR/SER 8 VDD 9 VDD 10 11 12 13 14 15 16 17 18 19 20 CS SDO DNC DNC SCK SDI D0 ENC+ ENC- D1 41 30 D7 29 D6 28 CLKOUT+ 27 CLKOUT- 26 OVDD 25 OGND 24 D5 23 D4 22 D3 21 D2 AIN+ 1 AIN- 2 GND 3 REFH 4 REFH 5 REFL 6 REFL 7 PAR/SER 8 VDD 9 VDD 10
40 39 38 37 36 35 34 33 32 31
UJ PACKAGE 40-LEAD (6mm x 6mm) PLASTIC QFN
UJ PACKAGE 40-LEAD (6mm x 6mm) PLASTIC QFN
TJMAX = 150C, JA = 32C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150C, JA = 32C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
DOUBLE DATA RATE LVDS OUTPUT MODE TOP VIEW D10_11+ D10_11- SENSE D8_9+ D0_1- D8_9- 30 D6_7+ 29 D6_7- 28 CLKOUT+ 27 CLKOUT- 41 26 OVDD 25 OGND 24 D4_5+ 23 D4_5- 22 D2_3+ 21 D2_3- 11 12 13 14 15 16 17 18 19 20 CS SDO DNC ENC+ ENC- DNC SCK SDI D0_1+ VREF VCM VDD OF+ OF-
40 39 38 37 36 35 34 33 32 31 AIN+ 1 AIN- 2 GND 3 REFH 4 REFH 5 REFL 6 REFL 7 PAR/SER 8 VDD 9 VDD 10
UJ PACKAGE 40-LEAD (6mm x 6mm) PLASTIC QFN
TJMAX = 150C, JA = 32C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
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LTC2262-12 ORDER INFORMATION
LEAD FREE FINISH LTC2262CUJ-12#PBF LTC2262IUJ-12#PBF TAPE AND REEL LTC2262CUJ-12#TRPBF LTC2262IUJ-12#TRPBF PART MARKING* LTC2262UJ-12 LTC2262UJ-12 PACKAGE DESCRIPTION 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 5)
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference External Reference Differential Analog Input (Note 6) Differential Analog Input (Note 7) Internal Reference External Reference CONDITIONS
l l l l l
MIN 12 -1 -0.4 -9 -1.5
TYP 0.3 0.1 1.5 1.5 0.4 20 30 10 0.3
MAX 1 0.4 9 1.5
UNITS Bits LSB LSB mV %FS %FS V/C ppm/C ppm/C LSBRMS
ANALOG INPUT
SYMBOL PARAMETER VIN VIN(CM) VSENSE IINCM IIN1 IIN2 IIN3 tAP tJITTER CMRR BW-3B
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) Per Pin, 150Msps 0 < AIN+, AIN- < VDD, No Encode 0 < PAR/SER < VDD 0.625V < SENSE < 1.3V
l l l l l l
MIN VCM - 100mV 0.625 -1 -3 -6
TYP 1 to 2 VCM 1.250 185
MAX VCM + 100mV 1.300 1 3 6
UNITS VP-P V V A A A A ns psRMS dB MHz
Analog Input Range (AIN+ - AIN-) Analog Input Common Mode (AIN+ + AIN-)/2 Analog Input Common Mode Current Analog Input Leakage Current PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth
External Voltage Reference Applied to SENSE External Reference Mode
0 0.17 80 Figure 6 Test Circuit 800
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LTC2262-12
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5)
SYMBOL SNR PARAMETER Signal-to-Noise Ratio CONDITIONS 5MHz Input 30MHz Input 70MHz Input 140MHz Input 5MHz Input 30MHz Input 70MHz Input 140MHz Input 5MHz Input 30MHz Input 70MHz Input 140MHz Input 5MHz Input 30MHz Input 70MHz Input 140MHz Input
l
DYNAMIC ACCURACY
MIN
TYP 70.5 70.4 70.3 70.1 88 88 82 81 90 90 90 90 70.4 70.3 70 69.8
MAX
UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
SFDR
Spurious Free Dynamic Range 2nd or 3rd Harmonic
l
Spurious Free Dynamic Range 4th Harmonic or Higher
l
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
l
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation -400A < IOUT < 1mA 1.7V < VDD < 1.9V -600A < IOUT < 1mA IOUT = 0 CONDITIONS IOUT = 0
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN 0.5 * VDD - 25mV TYP 0.5 * VDD 25 4 1.225 1.250 25 7 0.6 1.275 MAX 0.5 * VDD + 25mV UNITS V ppm/C V ppm/C mV/V
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC- ) Differential Encode Mode (ENC- Not Tied to GND) VID VICM VIN RIN CIN VIH VIL VIN RIN CIN Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Voltage Range Input Resistance Input Capacitance (Note 8)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS MIN TYP MAX UNITS
l l l
0.2 1.2 1.1 0.2 10 3.5 1.6 3.6
V V V V k pF V 0.6 V V k pF
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Internally Set Externally Set (Note 8) ENC+, ENC- to GND (See Figure 10) (Note 8) VDD = 1.8V VDD = 1.8V ENC+ to GND (See Figure 11) (Note 8)
Single-Ended Encode Mode (ENC- Tied to GND)
l l l
1.2 0 30 3.5 3.6
4
LTC2262-12 DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER DIGITAL INPUTS (CS, SDI, SCK) VIH VIL IIN CIN ROL IOH COUT High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance VDD = 1.8V VDD = 1.8V VIN = 0V to 3.6V (Note 8) VDD = 1.8V, SDO = 0V SDO = 0V to 3.6V (Note 8)
l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS MIN 1.3 0.6 -10 3 200 -10 4 10 10 TYP MAX UNITS V V A pF A pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) OVDD = 1.8V VOH VOL VOH VOL VOH VOL VOD VOS RTERM High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance IO = -500A IO = 500A IO = -500A IO = 500A IO = -500A IO = 500A 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V
l l l l
1.750
1.790 0.010 1.488 0.010 1.185 0.010 0.050
V V V V V V 454 1.375 mV mV V V
OVDD = 1.5V
OVDD = 1.2V
DIGITAL DATA OUTPUTS (LVDS MODE) 247 1.125 350 175 1.250 1.250 100
POWER REQUIREMENTS
SYMBOL PARAMETER VDD OVDD IVDD IOVDD PDISS Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current Power Dissipation
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9)
CONDITIONS (Note 10) (Note 10) DC Input Sine Wave Input Sine Wave Input, OVDD=1.2V DC Input Sine Wave Input, OVDD=1.2V
l l l l
MIN 1.7 1.1
TYP 1.8 80.9 82.7 5.1 146 155
MAX 1.9 1.9
UNITS V V mA mA mA mW mW
CMOS Output Modes: Full Data Rate and Double Data Rate
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LTC2262-12 POWER REQUIREMENTS
SYMBOL PARAMETER LVDS Output Mode VDD OVDD IVDD IOVDD PDISS Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current (0VDD = 1.8V) Power Dissipation (Note 10) (Note 10) Sine Wave Input Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode
l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9)
CONDITIONS MIN 1.7 1.7 86.3 18.8 36.7 189 221 0.5 9 10 TYP 1.8 MAX 1.9 1.9 UNITS V V mA mA mA mW mW mW mW mW
All Output Modes PSLEEP PNAP PDIFFCLK Sleep Mode Power Nap Mode Power Power Increase with Differential Encode Mode Enabled (No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS
SYMBOL fS tL tH tAP PARAMETER Sampling Frequency ENC Low Time (Note 8) ENC High Time (Note 8) Sample-and-Hold Acquisition Delay Time
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS (Note 10) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On
l l l l l
MIN 1 3.17 2.0 3.17 2.0
TYP 3.33 3.33 3.33 3.33 0
MAX 150 500 500 500 500
UNITS MHz ns ns ns ns ns
SYMBOL tD tC tSKEW
PARAMETER ENC to Data Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Pipeline Latency
CONDITIONS CL = 5pF (Note 8) CL = 5pF (Note 8) tD - tC (Note 8) Full Data Rate Mode Double Data Rate Mode CL = 5pF (Note 8) CL = 5pF (Note 8) tD - tC (Note 8)
l l l l l l
MIN 1.1 1 0
TYP 1.7 1.4 0.3 5.0 5.5
MAX 3.1 2.6 0.6
UNITS ns ns ns Cycles Cycles
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
Digital Data Outputs (LVDS Mode) tD tC tSKEW ENC to Data Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Pipeline Latency 1.1 1 0 1.8 1.5 0.3 5.5 3.2 2.7 0.6 ns ns ns Cycles
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LTC2262-12 TIMING CHARACTERISTICS
SYMBOL tSCK tS tH tDS tDH tDO PARAMETER SCK Period CS to SCK Setup Time SCK to CS Setup Time SDI Setup Time SDI Hold Time SCK Falling to SDO Valid Readback Mode, CSDO = 20pF RPULLUP = 2k , SPI Port Timing (Note 8) Write Mode Readback Mode, CSDO = 20pF RPULLUP = 2k ,
l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS MIN 40 250 5 5 5 5 125 TYP MAX UNITS ns ns ns ns ns ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 150MHz, LVDS outputs with internal termination disabled, differential ENC+/ENC- = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2's complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = 1.8V, fSAMPLE = 150MHz, ENC+ = single-ended 1.8V square wave, ENC- = 0V, input range = 2VP-P with differential drive, 5pF load on each digital output unless otherwise noted. Note 10: Recommended operating conditions.
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N tH tL ENC- ENC+ tD D0-D11, OF tC N-5 N-4 N-3 N-2 N-1 N+1 N+2 N+3 N+4
CLKOUT + CLKOUT -
226212 TD01
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LTC2262-12 TIMING DIAGRAMS
Double Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N tH tL ENC- ENC+ tD D0_1 D0N-5 D1N-5 D0N-4 tD D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 N+1 N+2 N+3 N+4
* * *
D10_11 D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 D10N-2 D11N-2
OF
OFN-5 tC
OFN-4 tC
OFN-3
OFN-2
CLKOUT+ CLKOUT -
226212 TD02
Double Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels
tAP ANALOG INPUT N tH tL ENC- ENC+ D0_1+ D0_1- D10_11+ D10_11- OF+ OF- CLKOUT+ CLKOUT - OFN-5 tC OFN-4 tC OFN-3 OFN-3 D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 D10N-2 D11N-2 tD D0N-5 D1N-5 D0N-4 tD D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 N+1 N+2 N+3 N+4
* * *
226212 TD03
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LTC2262-12 TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tS CS SCK tDO SDI SDO HIGH IMPEDANCE R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 tDS tDH tSCK tH
SPI Port Timing (Write Mode)
CS SCK
SDI SDO
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
226212 TD04
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2262-12: Integral Nonlinearity (INL)
1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
226212 G01
LTC2262-12: Differential Nonlinearity (DNL)
1.0 0.8 0.6 AMPLITUDE (dBFS) 0 1024 2048 3072 OUTPUT CODE 4096
226212 G02
LTC2262-12: 8k Point FFT, fIN = 5MHz -1dBFS, 150Msps
0 -10 -20 -30 -40 -50 -60 -70 -80
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
-90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60 70
226212 G03
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LTC2262-12 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2262-12: 8k Point FFT, fIN = 30MHz -1dBFS, 150Msps
0 -10 -20 -30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -50 -60 -70 -80 0 -10 -20 -30 -40 -50 -60 -70 -80 AMPLITUDE (dBFS) 0 20 30 40 50 FREQUENCY (MHz) 60 70
226212 G05
LTC2262-12: 8k Point FFT, fIN = 70MHz -1dBFS, 150Msps
0 -10 -20 -30 -40 -50 -60 -70 -80
LTC2262-12: 8k Point FFT, fIN = 140MHz -1dBFS, 150Msps
-90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60 70
226212 G04
-90 -100 -110 -120 10
-90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60 70
226212 G06
LTC2262-12: 8k Point 2-Tone FFT, fIN = 68MHz, 69MHz, -1dBFS, 150Msps
0 -10 -20 -30 AMPLITUDE (dBFS) -40 COUNT -50 -60 -70 -80 14000 12000 10000 8000 6000 4000 18000 16000
LTC2262-12: Shorted Input Histogram
72 71 70 SNR (dBFS) 69 68 67 2000 0 2044 66
LTC2262-12: SNR vs Input Frequency, -1dB, 2V Range, 150Msps
-90 -100 -110 -120 0 10 20 30 40 50 FREQUENCY (MHz) 60 70
226212 G07
2046 OUTPUT CODE
2048
226212 G08
0
50
100 150 200 250 300 INPUT FREQUENCY (MHz)
350
226212 G09
LTC2262-12: SFDR vs Input Frequency, -1dB, 2V Range, 150Msps
95 90 85 80 75 70 65 SFDR (dBc AND dBFS) 110 100 90 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350
LTC2262-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 150Msps
dBFS 90
LTC2262-12: IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB
85 LVDS OUTPUTS dBc IVDD (mA) 80
SFDR (dBFS)
75 CMOS OUTPUTS 70
0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
65
0
25
50 75 100 125 SAMPLE RATE (Msps)
150
226212 G10
226212 G12
226212 G13
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LTC2262-12 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2262-12: IOVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB, 5pF on Each Data Output
45 40 35 SNR (dBFS) 30 IOVDD (mA) 25 1.75mA LVDS 20 15 10 5 0 0 25 1.8V CMOS 1.2V CMOS 50 75 100 125 SAMPLE RATE (Msps) 150 68 67 3.5mA LVDS 70 70 SNR (dBFS) DDR CMOS 69 71
LTC2262-12: SNR vs SENSE, fIN = 5MHz, -1dB
71
LTC2262-12: SNR vs Sample Rate and Digital Output Mode, 30MHz Sine Wave Input, -1dB
LVDS CMOS
69
68
66
67 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 0 25 50 75 100 125 SAMPLE RATE (Msps) 150
226212 G14
226212 G15
226212 G18
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT MODES AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. GND (Pin 3): ADC Power Ground. REFH (Pins 4, 5): ADC High Reference. Bypass to Pins 6, 7 with a 2.2F ceramic capacitor and to ground with a 0.1F ceramic capacitor. REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins 4, 5 with a 2.2F ceramic capacitor and to ground with a 0.1F ceramic capacitor. PAR/SER (Pin 8): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. VDD (Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass to ground with 0.1F ceramic capacitors. Pins 9 and 10 can share a bypass capacitor. ENC+ (Pin 11): Encode Input. Conversion starts on the rising edge. ENC - (Pin 12): Encode Complement Input. Conversion starts on the falling edge. CS (Pin 13): In serial programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS controls the clock duty cycle stabilizer. When CS is low, the clock duty cycle stabilizer is turned off. When CS is high, the clock duty cycle stabilizer is turned on. CS can be driven with 1.8V to 3.3V logic. SCK (Pin 14): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = VDD), SCK controls the digital output mode. When SCK is low, the full-rate CMOS output mode is enabled. When SCK is high, the double data rate LVDS output mode (with 3.5mA output current) is enabled. SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 15): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. When SDI is low, the part operates normally. When SDI is high, the
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LTC2262-12 PIN FUNCTIONS
part enters sleep mode. SDI can be driven with 1.8V to 3.3V logic. SDO (Pin 16): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V-3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO is not used and should not be connected. OGND (Pin 25): Output Driver Ground. OVDD (Pin 26): Output Driver Supply. Bypass to ground with a 0.1F ceramic capacitor. VCM (Pin 37): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs. Bypass to ground with a 0.1F ceramic capacitor. VREF (Pin 38): Reference Voltage Output. Bypass to ground with a 1F ceramic capacitor, nominally 1.25V. SENSE (Pin 39): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a 1V input range. Connecting SENSE to ground selects the internal reference and a 0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of 0.8 * VSENSE. FULL-RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D0 to D11 (Pins 19-24, 29-34): Digital Outputs. D11 is the MSB. CLKOUT- (Pin 27): Inverted version of CLKOUT+. CLKOUT+ (Pin 28): Data Output Clock. The digital outputs normally transition at the same time as the falling edge of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. DNC (Pins 17, 18, 35): Do not connect these pins. OF (Pin 36): Over/Under Flow Digital Output. OF is high when an overflow or underflow has occurred. DOUBLE DATA RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D0_1 to D10_11 (Pins 20, 22, 24, 30, 32, 34): Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11) appear when CLKOUT+ is high. CLKOUT- (Pin 27): Inverted version of CLKOUT+. CLKOUT+ (Pin 28): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. DNC (Pins 17, 18, 19, 21, 23, 29, 31, 33, 35): Do not connect these pins. OF (Pin 36): Over/Under Flow Digital Output. OF is high when an overflow or underflow has occurred. DOUBLE DATA RATE LVDS OUTPUT MODE All Pins Below Have LVDS Output Levels. The Output Current Level is Programmable. There is an Optional Internal 100 Termination Resistor Between the Pins of Each LVDS Output Pair. D0_1-/D0_1+ to D10_11-/D10_11+ (Pins 19/20, 21/22, 23/24, 29/30, 31/32, 33/34): Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11) appear when CLKOUT+ is high. CLKOUT-/CLKOUT+ (Pins 27/28): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. OF-/OF+ (Pins 35/36): Over/Under Flow Digital Output. OF+ is high when an overflow or underflow has occurred.
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LTC2262-12 FUNCTIONAL BLOCK DIAGRAM
AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE VDD GND AIN- VCM 0.1F VREF 1F RANGE SELECT 1.25V REFERENCE
VDD/2
SHIFT REGISTER AND CORRECTION
SENSE
REF BUF
REFH
REFL INTERNAL CLOCK SIGNALS OVDD OF D11
DIFF REF AMP
CLOCK/DUTY CYCLE CONTROL
MODE CONTROL REGISTERS
OUTPUT DRIVERS
* * * D0 CLKOUT + CLKOUT -
REFH
0.1F
REFL ENC
+
OGND ENC- PAR/SER CS SCK SDI SDO
226212 F01
2.2F 0.1F 0.1F
Figure 1. Functional Block Diagram
APPLICATIONS INFORMATION
CONVERTER OPERATION The LTC2262-12 is a low power 12-bit 150Msps A/D converter that is powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially or single-ended for lower power consumption. The digital outputs can be CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) Many additional features can be chosen by programming the mode control registers through a serial SPI port. See the Serial Programming Mode section. ANALOG INPUT The analog input is a differential CMOS sample-and-hold circuit (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM output
AIN
+
LTC2262-12 VDD 10 CPARASITIC 1.8pF RON 25 CPARASITIC 1.8pF VDD RON 25
CSAMPLE 3.5pF
VDD 10
CSAMPLE 3.5pF
AIN-
1.2V 10k ENC+ ENC- 10k 1.2V
226212 F02
Figure 2. Equivalent Input Circuit
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LTC2262-12 APPLICATIONS INFORMATION
pin, which is nominally VDD/2. For the 2V input range, the inputs should swing from VCM - 0.5V to VCM + 0.5V. There should be 180 phase difference between the inputs. INPUT DRIVE CIRCUITS Input filtering If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application's input frequency.
50 VCM 0.1F 0.1F ANALOG INPUT T1 1:1 25 25 25 0.1F 12pF 25 AIN-
226212 F03
Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion.
50
VCM 0.1F
0.1F ANALOG INPUT T2 T1 25 25 0.1F
AIN+ LTC2262-12 1.8pF
0.1F
AIN-
226212 F05
AIN+ LTC2262-12
T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 5. Recommended Front-End Circuit for Input Frequencies from 170MHz to 270MHz
T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
50
Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz
ANALOG INPUT
VCM 0.1F
0.1F
2.7nH 25 T1 0.1F
AIN+ LTC2262-12
50
VCM 0.1F
0.1F
25
2.7nH
AIN-
226212 F06
0.1F ANALOG INPUT T2 T1 25 25 0.1F
AIN+ LTC2262-12 4.7pF
T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
0.1F
AIN
-
Figure 6. Recommended Front-End Circuit for Input Frequencies Above 270MHz
226212 F04
T1: MA/COM MABA-007159-000000 T2: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 4. Recommended Front-End Circuit for Input Frequencies from 70MHz to 170MHz
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LTC2262-12 APPLICATIONS INFORMATION
Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC coupled to the A/D so the amplifier's output common mode voltage can be optimally set to minimize distortion. At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D. Reference The LTC2262-12 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the external reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9.) The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 * VSENSE.
TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 * VSENSE FOR 0.65V < VSENSE < 1.300V 0.1F REFH SENSE BUFFER INTERNAL ADC HIGH REFERENCE
The VREF , REFH and REFL pins should be bypassed as shown in Figure 8. The 0.1F capacitor between REFH and REFL should be as close to the pins as possible (not on the back side of the circuit board).
LTC2262-12 1.25V VREF 1F 0.625V RANGE DETECT AND CONTROL 5 1.25V BANDGAP REFERENCE
2.2F
0.1F
0.8x DIFF AMP
0.1F REFL INTERNAL ADC LOW REFERENCE
VCM HIGH SPEED DIFFERENTIAL 0.1F AMPLIFIER ANALOG INPUT 200 200 25 0.1F AIN+ LTC2262-12 12pF VREF 0.1F
226212 F08
Figure 8. Reference Circuit
+ -
+ -
25
AIN- 12pF 1.25V EXTERNAL REFERENCE
1F LTC2262-12
226212 F07
SENSE 1F
226212 F09
Figure 7. Front-End Circuit Using a High Speed Differential Amplifier
Figure 9. Using an External 1.25V Reference
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LTC2262-12 APPLICATIONS INFORMATION
Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals--do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10) and the single-ended encode mode (Figure 11). The differential encode mode is recommended for sinusoidal, PECL or LVDS encode inputs (Figures 12, 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC- should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ and ENC- should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC - is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. Clock Duty Cycle Stabilizer For good performance the encode signal should have a 50%(5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the encode signal changes frequency or is turned off, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. The duty cycle stabilizer is enabled by mode control register A2 (serial programming mode), or by CS (parallel programming mode).
LTC2262-12
VDD DIFFERENTIAL COMPARATOR
25
0.1F T1 1:4
ENC+ 100 LTC2262-12 100 ENC- 0.1F
226212 F12
VDD
D1
15k ENC+ ENC- 30k T1: COILCRAFT WBC4 - 1WL D1: AVAGO HSMS - 2822 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
226212 F10
Figure 12. Sinusoidal Encode Drive
Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode
0.1F ENC+
LTC2262-12 1.8V TO 3.3V 0V ENC+ ENC- 30k CMOS LOGIC BUFFER
226212 F11
PECL OR LVDS CLOCK
LTC2262-12 0.1F ENC-
226212 F13
Figure 13. PECL or LVDS Encode Drive
Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode
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LTC2262-12 APPLICATIONS INFORMATION
For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50%(5%) duty cycle. The duty cycle stabilizer should not be used below 5Msps. DIGITAL OUTPUTS Digital Output Modes The LTC2262-12 can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system). The output mode is set by mode control register A3 (serial programming mode), or by SCK (parallel programming mode). Note that double data rate CMOS cannot be selected in the parallel programming mode. Full-Rate CMOS Mode In full-rate CMOS mode the 12 digital outputs (D0-D11), overflow (OF), and the data output clocks (CLKOUT+, CLKOUT-) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. Double Data Rate CMOS Mode In double data rate CMOS mode, two data bits are multiplexed and output on each data pin. This reduces the number of data lines by seven, simplifying board routing and reducing the number of input pins needed to receive the data. The 6 digital outputs (D0_1, D2_3, D4_5, D6_7, D8_9, D10_11), overflow (OF), and the data output clocks (CLKOUT+, CLKOUT-) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used.
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When using double data rate CMOS at high sample rates the SNR will degrade slightly (see Typical Performance Characteristics section). DDR CMOS is not recommended for sample frequencies above 100Msps. Double Data Rate LVDS Mode In double data rate LVDS mode, two data bits are multiplexed and output on each differential output pair. There are 6 LVDS output pairs (D0_1+/D0_1- through D10_11+/D10_11-) for the digital output data. Overflow (OF+/OF -) and the data output clock (CLKOUT+/CLKOUT-) each have an LVDS output pair. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100 differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. In LVDS mode, OVDD must be 1.8V. Programmable LVDS Output Current In LVDS mode, the default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases using just an external 100 termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100 termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is increased by 1.6x to maintain about the same output voltage swing.
17
LTC2262-12 APPLICATIONS INFORMATION
Overflow Bit The overflow output bit (OF) outputs a logic high when the analog input is either overranged or underranged. The overflow bit has the same pipeline latency as the data bits. Phase Shifting the Output Clock In full-rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT+, so the rising edge of CLKOUT+ can be used to latch the output data. In double data rate CMOS and LVDS modes the data output bits normally change at the same time as the falling and rising edges of CLKOUT+. To allow adequate setup-and-hold time when latching the data, the CLKOUT+ signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The LTC2262-12 can also phase shift the CLKOUT- signals by serially programming mode control register A2. The output clock can be shifted by 0, 45, 90 or 135. To use the phase shifting feature the clock duty cycle stabilizer must be turned on. CLKOUT+/ Another control register bit can invert the polarity of CLKOUT+ and CLKOUT-, independently of the phase shift. The combination of these two features enables phase shifts of 45 up to 315 (Figure 14). DATA FORMAT Table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2's complement format can be selected by serially programming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ - AIN- (2V RANGE) >+1.000000V +0.999512V +0.999024V +0.000488V 0.000000V -0.000488V -0.000976V -0.999512V -1.000000V -1.000000V OF 1 0 0 0 0 0 0 0 0 1 D11-D0 (OFFSET BINARY) 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 D11-D0 (2's COMPLEMENT) 0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000
ENC+
D0-D11, OF PHASE SHIFT 0 45 90 135 CLKOUT+ 180 225 270 315
226212 F14
MODE CONTROL BITS CLKINV 0 0 0 0 1 1 1 1 CLKPHASE1 0 0 1 1 0 0 1 1 CLKPHASE0 0 1 0 1 0 1 0 1
Figure 14. Phase Shifting CLKOUT
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LTC2262-12 APPLICATIONS INFORMATION
Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. The digital output is "randomized" by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied--an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially programming mode control register A4. Alternate Bit Polarity Another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11) are inverted before the output buffers. The even bits (D0, D2, D4, D6, D8, D10), OF and CLKOUT are not affected. This can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. When there is a very small signal at the input of the A/D that is centered around midscale, the digital outputs toggle between mostly 1s and mostly 0s. This simultaneous switching of most of the bits will cause large currents in the ground plane. By inverting every other bit, the alternate bit polarity mode makes half of the bits transition high while half of the bits transition low. To first order, this cancels current flow in the ground plane, reducing the digital noise.
PC BOARD OF OF CLKOUT FPGA
CLKOUT
CLKOUT
D11
D11/D0
OF
D10
D10/D0
D11/D0 D11 D10/D0
D2 RANDOMIZER ON D1
* * *
D2/D0 LTC2262-12
D10 D2/D0
D1/D0
* * *
D2
D1/D0 D0 D0
226212 F15
D1 D0 D0
Figure 15. Functional Equivalent of Digital Output Randomizer
226212 F15
Figure 16. Unrandomizing a Randomized Digital Output Signal
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LTC2262-12 APPLICATIONS INFORMATION
The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit polarity mode is independent of the digital output randomizer--either, both or neither function can be on at the same time. When alternate bit polarity mode is on, the data format is offset binary and the 2's complement control bit has no effect. The alternate bit polarity mode is enabled by serially programming mode control register A4. Digital Output Test Patterns To allow in-circuit testing of the digital interface to the A/D, there are several test modes that force the A/D data outputs (OF, D11-D0) to known values: All 1s: All outputs are 1 All 0s: All outputs are 0 Alternating: Outputs change from all 1s to all 0s on alternating samples Checkerboard: Outputs change from 1010101010101 to 0101010101010 on alternating samples The digital output test patterns are enabled by serially programming mode control register A4. When enabled, the test patterns override all other formatting modes: 2's complement, randomizer, alternate-bit-polarity. Output Disable The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high impedance disabled state is intended for long periods of inactivity--it is too slow to multiplex a data bus between multiple converters at full speed. Sleep and Nap Modes The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire A/D converter is powered down, resulting in 0.5mW power consumption. Sleep mode is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode). The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF , REFH, and REFL. For the suggested values in Figure 8, the A/D will stabilize after 2ms. In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wake-up than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50s should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Nap mode is enabled by mode control register A1 in the serial programming mode. DEVICE PROGRAMMING MODES The operating modes of the LTC2262-12 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK and SDI pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V or 3.3V CMOS logic. Table 2 shows the modes set by CS, SCK and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN CS DESCRIPTION Clock Duty Cycle Stabilizer Control Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On SCK Digital Output Mode Control Bit 0 = Full-Rate CMOS Output Mode 1 = Double Data Rate LVDS Output Mode (3.5mA LVDS Current, Internal Termination Off) SDI Power Down Control Bit 0 = Normal Operation 1 = Sleep Mode
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LTC2262-12 APPLICATIONS INFORMATION
Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the timing
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 RESET Bit 7 RESET D6 X D5 X Software Reset Bit D4 X D3 X D2 X D1 X D0 X
diagrams). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open-drain output that pulls to ground with a 200 impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero.
0 = Not Used 1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero After the Reset is Complete Bits 6-0 Unused, Don't Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h) D7 X Bits 7-2 Bits 1-0 D6 X Unused, Don't Care Bits. PWROFF1:PWROFF0 00 = Normal Operation 01 = Nap Mode 10 = Not Used 11 = Sleep Mode Power Down Control Bits D5 X D4 X D3 X D2 X D1 PWROFF1 D0 PWROFF0
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LTC2262-12 APPLICATIONS INFORMATION
REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 X Bits 7-4 Bit 3 D6 X Unused, Don't Care Bits. CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams) 1 = Inverted CLKOUT Polarity CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits 00 = No CLKOUT Delay (As Shown in the Timing Diagrams) 01 = CLKOUT+/CLKOUT- Delayed by 45 (Clock Period * 1/8) 10 = CLKOUT+/CLKOUT- Delayed by 90 (Clock Period * 1/4) 11 = CLKOUT+/CLKOUT- Delayed by 135 (Clock Period * 3/8) Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On DCS Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On D5 X D4 X D3 CLKINV D2 CLKPHASE1 D1 CLKPHASE0 D0 DCS
Bits 2-1
Bit 0
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 X Bit 7 Bits 6-4 D6 ILVDS2 Unused, Don't Care Bit. ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 1.6x the Current Set by ILVDS2:ILVDS0 OUTOFF Output Disable Bit 0 = Digital Outputs are Enabled 1 = Digital Outputs are Disabled and Have High Output Impedance OUTMODE1:OUTMODE0 Digital Output Mode Control Bits 00 = Full-Rate CMOS Output Mode 01 = Double Data Rate LVDS Output Mode 10 = Double Data Rate CMOS Output Mode 11 = Not Used D5 ILVDS1 D4 ILVDS0 D3 TERMON D2 OUTOFF D1 OUTMODE1 D0 OUTMODE0
Bit 3
Bit 2
Bits 1-0
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LTC2262-12 APPLICATIONS INFORMATION
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 X Bit 7-6 Bits 5-3 D6 X Unused, Don't Care Bits. OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = Digital Output Test Patterns Off 001 = All Digital Outputs = 0 011 = All Digital Outputs = 1 101 = Checkerboard Output Pattern. OF D11-D0 Alternate Between 1 0101 1010 0101 and 0 1010 0101 1010 , 111 = Alternating Output Pattern. OF D11-D0 Alternate Between 0 0000 0000 0000 and 1 1111 1111 1111 , Note: Other Bit Combinations are not Used ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On TWOSCOMP Two's Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two's Complement Data Format Note: ABP = 1 forces the output format to be Offset Binary D5 OUTTEST2 D4 OUTTEST1 D3 OUTTEST0 D2 ABP D1 RAND D0 TWOSCOMP
Bit 2
Bit 1
Bit 0
GROUNDING AND BYPASSING The LTC2262-12 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1F capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The larger 2.2F capacitor between REFH and REFL can be somewhat further away.
The VCM capacitor should be located as close to the pin as possible. To make space for this the capacitor on VREF can be further away or on the back of the PC board. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC2262-12 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board.
226212p
23
LTC2262-12 TYPICAL APPLICATIONS
LTC2262 Evaluation Board Schematic
T2 MABAES0060
R9 10 R39 33.2 1% R40 33.2 1%
*
ANALOG INPUT
*
SENSE C23 1F C51 4.7pF C17 1F R14 1k
R10 10 R15 100 C12 0.1F
R16 100
C13 1F
C19 0.1F 40 39 38 37 36 OF+ 35 OF- 34 33 32 D9 31 D8 30 29 28 27 26 25 24 23 22 21 VDD SENSE VREF VCM R27 10 1 R28 10 2 3 4 C15 0.1F 5 C20 2.2F 6 7 C21 0.1F PAR/SER 8 9 10 C18 0.1F AIN+ AIN- GND REFH REFH REFL REFL PAR/SER VDD VDD GND 41 ENC+ ENC- 11 12 CS 13 SCK 14 SDI SDO DNC DNC 15 16 17 18 D0 19 LTC2262CUJ D11 D10
DIGITAL OUTPUTS
D7 D6 CLKOUT+ CLKOUT- OVDD OGND D5 D4 D3 D2 D1 20
0VDD C37 0.1F
DIGITAL OUTPUTS
ENCODE CLOCK
R13 100
226212 TA02
SPI BUS
226212p
24
LTC2262-12 TYPICAL APPLICATIONS
Silkscreen Top Top Side
226212 TA04 226212 TA03
Inner Layer 2 GND
Inner Layer 3
226212 TA05
226212 TA06
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25
LTC2262-12 TYPICAL APPLICATIONS
Inner Layer 4 Inner Layer 5 Power
226212 TA07
226212 TA08
Bottom Side
226212 TA09
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26
LTC2262-12 PACKAGE DESCRIPTION
UJ Package 40-Lead Plastic QFN (6mm x 6mm)
(Reference LTC DWG # 05-08-1728 Rev O)
0.70 0.05
6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES)
4.42 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 0.10 (4 SIDES)
0.75 0.05 R = 0.10 TYP
R = 0.115 TYP
39 40 0.40 0.10 1 PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 2
PIN 1 TOP MARK (SEE NOTE 6)
4.50 REF (4-SIDES)
4.42 0.10
4.42 0.10
(UJ40) QFN REV O 0406
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
226212p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2262-12 RELATED PARTS
PART NUMBER LTC1993-2 LTC1994 LTC2202 LTC2203 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2209 LTC2220 LTC2220-1 LTC2224 LTC2249 LTC2250 LTC2251 LTC2252 LTC2253 LTC2254 LTC2255 LTC2256-12/ LTC2257-12/ LTC2258-12 LTC2259-12/ LTC2260-12/ LTC2261-12 LTC2262-14 LTC2284 LTC2299 LTC5517 LTC5527 LTC5557 LTC5575 LTC6400-20 LTC6604-2.5/ LTC6604 -5/ LTC6604-10/ LTC6604-15 DESCRIPTION High Speed Differential Op Amp Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 16-Bit, 40Msps, 3.3V ADC 16-Bit, 65Msps, 3.3V ADC 16-Bit, 80Msps, 3.3V ADC 16-Bit, 105Msps, 3.3V ADC 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 16-Bit, 160Msps, 3.3V ADC, LVDS Outputs 12-Bit, 170Msps ADC 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 14-Bit, 80Msps ADC 10-Bit, 105Msps ADC 10-Bit, 125Msps ADC 12-Bit, 105Msps ADC 12-Bit, 125Msps ADC 14-Bit, 105Msps ADC 14-Bit, 125Msps, 3V ADC, Lowest Power 12-Bit, 25/40/65Msps 1.8V ADCs, Ultralow Power COMMENTS 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain Low Distortion: -94dBc at 1MHz 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN 590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN 1450mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN 890mW, 67.5dB SNR, 9mm x 9mm QFN Package 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN 230mW, 73dB SNR, 5mm x 5mm QFN Package 320mW, 61.6dB SNR, 5mm x 5mm QFN Package 395mW, 61.6dB SNR, 5mm x 5mm QFN Package 320mW, 70.2dB SNR, 5mm x 5mm QFN Package 395mW, 70.2dB SNR, 5mm x 5mm QFN Package 320mW, 72.5dB SNR, 5mm x 5mm QFN Package 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN 34mW/47mW/ 71.1dB SNR, 88dB SFDR DDR LVDS/DDR CMOS/CMOS Outputs, 6mm x 6mm QFN Package 87mW/103mW/124mW, 70.8dB SNR, 85dB SFDR DDR LVDS/DDR CMOS/CMOS Outputs, 6mm x 6mm QFN Package 149mW, 72.8dB SNR, 88dB SFDR DDR LVDS/DDR CMOS/CMOS Outputs, 6mm x 6mm QFN Package 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN 230mW, 71.6dB SNR, 5mm x 5mm QFN Package High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports 23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply Operation, Integrated Transformer High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator Integrated RF and LO Transformer Fixed Gain 10V/V, 2.1nVHz Total Input Noise, 3mm x 3mm QFN-16 Package Dual Matched 4th Order LP Filters with Differential Drivers. Low Noise, Low Distortion Amplifiers
12-Bit, 80/105/125Msps 1.8V ADCs, Ultralow Power
14-Bit, 150Msps 1.8V ADCs, Ultralow Power 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk Dual 14-Bit, 80Msps ADC 40MHz to 900MHz Direct Conversion Quadrature Demodulator 400MHz to 3.7GHz High Linearity Downconverting Mixer 400MHz to 3.8GHz High Linearity Downconverting Mixer 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator 1.8GHz Low Noise, Low Distortion Differential ADC Driver for 300MHz IF Dual Matched 2.5MHz, 5MHz, 10MHz, 15MHz Filter with ADC Driver
226212p
28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0309 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2009

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